279 lines
8.6 KiB
C
279 lines
8.6 KiB
C
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/************************************************Copyright(c)***********************************
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** Quintic(Nanjing) Microelectronics Co,Ltd.
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**
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** http://www.quinticcorp.com
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**
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**--------------------File Info----------------------------------------------------------------
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** File Name: qndriver.h
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** subversion number: 160
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**----------------------------------------------------------------------------------------
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************************************************************************************************/
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#ifndef _QN_0835_H
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#define _QN_0835_H
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#if(TCFG_FM_QN8035_ENABLE == ENABLE)
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#define PILOT_CCA 1 // 0: disable stereo judgement for the country has many mono FM stations
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#define CCA_PILOT_SNR_FILTER 35 //25
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#define FREQ2CHREG(freq) ((freq-6000)/5)
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/**********************************QN8035's clock source selection**************
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1.QN8035's default clock source is 32768HZ.
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2.setting QN8035's clock source and clock source type(like sine-wave clock or digital clock).
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3.user need to modify clock source according to actual hardware platform.
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4.clock formula,the details please refer to the QN8035's datasheet
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XTAL_DIV = Round(Clock/32768);
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PLL_DLT = Round((28500000*512*XTAL_DIV)/Clock)-442368
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*******************************************************************************/
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#define QND_SINE_WAVE_CLOCK 0x00 //inject sine-wave clock
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#define QND_DIGITAL_CLOCK 0x80 //inject digital clock,default is inject digital clock
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//crystal clock is 32768HZ
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#define QND_XTAL_DIV0 0x01
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#define QND_XTAL_DIV1 0x08
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#define QND_XTAL_DIV2 0x5C
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/*
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//crystal clock is 32768HZ
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#define QND_XTAL_DIV0 0x01
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#define QND_XTAL_DIV1 0x08
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#define QND_XTAL_DIV2 0x5C
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//crystal clock is 1MHZ
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#define QND_XTAL_DIV0 0x1F
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#define QND_XTAL_DIV1 0x00
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#define QND_XTAL_DIV2 0x38
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//crystal clock is 4MHZ
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#define QND_XTAL_DIV0 0x7A
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#define QND_XTAL_DIV1 0x00
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 6MHZ
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#define QND_XTAL_DIV0 0xB7
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#define QND_XTAL_DIV1 0x00
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 7.3728MHZ
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#define QND_XTAL_DIV0 0xE1
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#define QND_XTAL_DIV1 0x08
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#define QND_XTAL_DIV2 0x5C
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//crystal clock is 8MHZ
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#define QND_XTAL_DIV0 0xF4
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#define QND_XTAL_DIV1 0x00
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 10MHZ
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#define QND_XTAL_DIV0 0x31
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#define QND_XTAL_DIV1 0x01
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 11.0592MHZ
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#define QND_XTAL_DIV0 0x52
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#define QND_XTAL_DIV1 0xA1
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#define QND_XTAL_DIV2 0x70
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//crystal clock is 12MHZ
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#define QND_XTAL_DIV0 0x6E
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#define QND_XTAL_DIV1 0x01
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 16MHZ
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#define QND_XTAL_DIV0 0xE8
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#define QND_XTAL_DIV1 0x01
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 20MHZ
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#define QND_XTAL_DIV0 0x62
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#define QND_XTAL_DIV1 0x02
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 24MHZ
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#define QND_XTAL_DIV0 0xDC
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#define QND_XTAL_DIV1 0x02
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#define QND_XTAL_DIV2 0x54
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//crystal clock is 26MHZ
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#define QND_XTAL_DIV0 0x19
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#define QND_XTAL_DIV1 0x03
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#define QND_XTAL_DIV2 0x54
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*/
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//following is definition step
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#define QND_STEP_CONSTANT 0x40 //(QND_FSTEP_100KHZ << 6)
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#define CHIPID_QN8035 0x84
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#define R_TXRX_MASK 0x30
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#define QND_MODE_SLEEP 0
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#define QND_MODE_WAKEUP 1
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// RX / TX value is using upper 8 bit
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#define QND_MODE_RX 0x8000
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#define QND_MODE_TX 0x4000
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#define QND_MODE_FM 0x0000
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#define QND_CONFIG_VOLUME 0x07
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#define CHIPSUBID_QN8035A0 0x01
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#define CHIPSUBID_QN8035A1 0x02
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enum {
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CCA_SENSITIVITY_LEVEL_0 = 0x1E06,
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CCA_SENSITIVITY_LEVEL_1 = 0x1E07, //if using the pilot as CCA,reference this item.
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CCA_SENSITIVITY_LEVEL_2 = 0x1E08,
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CCA_SENSITIVITY_LEVEL_3 = 0x1E09,
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CCA_SENSITIVITY_LEVEL_4 = 0x1E0A, //if not using the pilot as CCA,reference this item.
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CCA_SENSITIVITY_LEVEL_5 = 0x1E0B,
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CCA_SENSITIVITY_LEVEL_6 = 0x1E0C,
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CCA_SENSITIVITY_LEVEL_7 = 0x1E0D,
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CCA_SENSITIVITY_LEVEL_8 = 0x1E0E,
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CCA_SENSITIVITY_LEVEL_9 = 0x1E0F
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};
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/**********************************************************************************************
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// Performance configuration
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***********************************************************************************************/
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#define SMSTART_VAL 12//19
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#define HCCSTART_VAL 18//33
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#define SNCSTART_VAL 51//55
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/**********************************************************************************************
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// limitation configuration
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***********************************************************************************************/
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//#define CCA_PILOT_SNR_FILTER 20//18
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#define CCA_PILOT_READ_DELAY 80//60
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#define CCA_PILOT_READ_COUNT 12//10
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#define CCA_PILOT_READ_COUNT_DELAY 5// 2
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#define CCA_PILOT_TH 3
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#define CCA_TIME_OUT 200
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/**********************************************************************************************
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definition register
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**********************************************************************************************/
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#define SYSTEM1 0x00
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#define CCA 0x01
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#define SNR 0x02
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#define RSSISIG 0x03
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#define STATUS1 0x04
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#define CID1 0x05
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#define CID2 0x06
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#define CH 0x07
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#define CH_START 0x08
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#define CH_STOP 0x09
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#define CH_STEP 0x0A
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#define RDSD0 0x0B
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#define RDSD1 0x0C
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#define RDSD2 0x0D
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#define RDSD3 0x0E
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#define RDSD4 0x0F
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#define RDSD5 0x10
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#define RDSD6 0x11
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#define RDSD7 0x12
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#define STATUS2 0x13
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#define VOL_CTL 0x14
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#define XTAL_DIV0 0x15
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#define XTAL_DIV1 0x16
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#define XTAL_DIV2 0x17
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#define INT_CTRL 0x18
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#define SMP_HLD_THRD 0x19
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#define RXAGC_GAIN 0x1A
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#define GAIN_SEL 0x1B
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#define SYSTEM_CTL1 0x1C
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#define SYSTEM_CTL2 0x1D
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#define RDSCOSTAS 0x1E
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#define REG_TEST 0x1F
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#define STATUS4 0x20
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#define RDSAGC2 0x21
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#define CCA1 0x27
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#define CCA2 0x28
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#define CCA3 0x29
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#define CCA4 0x2A
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#define CCA5 0x2B
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#define PLT1 0X2F
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#define PLT2 0x30
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#define SMSTART 0x34
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#define SNCSTART 0x35
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#define HCCSTART 0x36
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#define CCA_CNT1 0x37
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#define CCA_CNT2 0x38
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#define CCA_SNR_TH_1 0x39
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#define CCA_SNR_TH_2 0x3A
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#define NCCFIR3 0x40
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#define REG_REF 0x49
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#define REG_DAC 0x4C
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/*******************************************************************************
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definition operation bit of register
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*******************************************************************************/
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#define CCA_CH_DIS 0x01
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#define CHSC 0x02
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#define RDSEN 0x08
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#define CH_CH 0x03
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#define CH_CH_START 0x0c
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#define CH_CH_STOP 0x30
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#define STNBY_MODE 0x20
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#define RX_MODE 0x10
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#define IMR 0x40
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#define RDS_RXUPD 0x80
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#define ST_MO_RX 0x01
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#define STNBY_RX_MASK 0x30
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#define RXCCA_MASK 0x03
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#define RX_CCA 0x02
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#define RXCCA_FAIL 0x08
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#define RX_MONO 0x04
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#define ICPREF 0x0F
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#define QND_READ(adr) QND_ReadReg(adr)
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#define QND_WRITE(adr, value) QND_WriteReg(adr, value)
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void QNF_SetRegBit(u8 reg, u8 bitMask, u8 data_val);
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u8 QND_ScanNoiseFloor(u16 start, u16 stop);
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void QND_RXSetTH(void);
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void QND_SetVol(u8 vol);
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bool QND_RXValidCH(u16 freq);
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u8 qn8035_init(void *priv);
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u8 qn8035_set_fre(void *priv, u16 freq);
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u8 qn8035_mute(void *priv, u8 On);
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u8 qn8035_read_id(void *priv);
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u8 qn8035_powerdown(void *priv);
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void qn8035_setch(u8 db);
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//extern _no_init bool _bit qn8035_online;
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#define QN_IIC_read(a) \
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QND_ReadReg(a)
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#endif
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#endif
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