306 lines
9.3 KiB
C
306 lines
9.3 KiB
C
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//*********************************************************************************//
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// Module name : csfr.h //
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// Description : q32DSP core sfr define //
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// By Designer : zequan_liu //
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// Dat changed : //
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//*********************************************************************************//
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#ifndef __Q32DSP_CSFR__
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#define __Q32DSP_CSFR__
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#define __RW volatile // read write
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#define __RO volatile const // only read
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#define __WO volatile // only write
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#define __u8 unsigned int // u8 to u32 special for struct
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#define __u16 unsigned int // u16 to u32 special for struct
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#define __u32 unsigned int
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//*********************************************************************************
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//
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// hcore_sfr
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//
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//*********************************************************************************
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#define csfr_base 0x100000
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//............. 0x0000 - 0x00ff............
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// typedef struct {
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// __RO __u32 SOFT_INT;
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// __WO __u32 SOFT_SET;
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// __WO __u32 SOFT_CLR;
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// __RW __u32 CON;
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// } JL_CMNG_TypeDef;
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//
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// #define JL_CMNG_BASE (csfr_base + map_adr(0x00, 0x00))
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// #define JL_CMNG ((JL_CMNG_TypeDef *)JL_CMNG_BASE)
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//............. 0x0100 - 0x01ff............
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typedef struct {
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__RW __u32 CON;
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__RW __u32 KEY;
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} JL_SDTAP_TypeDef;
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#define JL_SDTAP_BASE (csfr_base + map_adr(0x01, 0x00))
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#define JL_SDTAP ((JL_SDTAP_TypeDef *)JL_SDTAP_BASE)
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//............. 0x0200 - 0x02ff............
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//............. 0x0300 - 0x03ff............ for mmu
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typedef struct {
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short page: 13;
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short vld: 1;
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short reserved: 2;
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} __attribute__((packed)) JL_MMU_TLB1_TypeDef;
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#define JL_MMU_TLB1 ((JL_MMU_TLB1_TypeDef *)(JL_MMU->TLB1_BEG))
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typedef struct {
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__RW __u32 CON;
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__RW __u32 TLB1_BEG;
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__RW __u32 TLB1_END;
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} JL_MMU_TypeDef;
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#define JL_MMU_BASE (csfr_base + map_adr(0x03, 0x00))
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#define JL_MMU ((JL_MMU_TypeDef *)JL_MMU_BASE)
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//............. 0x1000 - 0x10ff............ for debug
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typedef struct {
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__RW __u32 CON;
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__RW __u32 RING_OSC;
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__RW __u32 CPASS_CON;
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__RW __u32 CPASS_ADRH;
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__RW __u32 CPASS_ADRL;
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__RW __u32 CPASS_BUF_LAST;
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__RW __u32 CPREFETCH_ADRH;
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__RW __u32 CPREFETCH_ADRL;
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__RO __u32 CACHE_MSG_CH;
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__RW __u32 MEM_CON;
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} JL_DSP_TypeDef;
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#define JL_DSP_BASE (csfr_base + map_adr(0x10, 0x00))
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#define JL_DSP ((JL_DSP_TypeDef*)JL_DSP_BASE)
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typedef struct {
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__RW __u32 DSP_BF_CON;
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__RW __u32 WR_EN;
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__RO __u32 MSG;
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__WO __u32 MSG_CLR;
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__RW __u32 CPU_WR_LIMH;
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__RW __u32 CPU_WR_LIML;
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__RW __u32 PRP_WR_LIMH;
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__RW __u32 PRP_WR_LIML;
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__RO __u32 PRP_MMU_MSG;
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__RO __u32 LSB_MMU_MSG_CH;
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__RO __u32 PRP_WR_LIMIT_MSG;
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__RO __u32 LSB_WR_LIMIT_CH;
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__RW __u32 CPU_PC_LIMH0;
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__RW __u32 CPU_PC_LIML0;
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__RW __u32 CPU_PC_LIMH1;
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__RW __u32 CPU_PC_LIML1;
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__RW __u32 PRP_SRM_INV_MSG;
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__RW __u32 LSB_SRM_INV_CH;
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} JL_DEBUG_TypeDef;
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#define JL_DEBUG_BASE (csfr_base + map_adr(0x10, 0x10))
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#define JL_DEBUG ((JL_DEBUG_TypeDef *)JL_DEBUG_BASE)
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//............. 0x2000 - 0x20ff............ for fft
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typedef struct {
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__RW __u32 CON;
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__RW __u32 CADR;
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__RW __u32 TEST0;
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__RW __u32 TEST1;
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} JL_FFT_TypeDef;
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#define JL_FFT_BASE (csfr_base + map_adr(0x20, 0x00))
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#define JL_FFT ((JL_FFT_TypeDef *)JL_FFT_BASE)
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//*********************************************************************************
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//
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// q32DSP_sfr
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//
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//*********************************************************************************
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//---------------------------------------------//
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// q32DSP define
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//---------------------------------------------//
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#define q32DSP_sfr_offset 0x010000
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#define q32DSP_sfr_base (csfr_base + 0xf000)
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#define q32DSP_cpu_base (q32DSP_sfr_base + 0x00)
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#define q32DSP_mpu_base (q32DSP_sfr_base + 0x80)
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#define q32DSP(n) ((JL_TypeDef_q32DSP *)(q32DSP_sfr_base + q32DSP_sfr_offset*n))
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#define q32DSP_mpu(n) ((JL_TypeDef_q32DSP_MPU *)(q32DSP_mpu_base + q32DSP_sfr_offset*n))
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//---------------------------------------------//
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// q32DSP core sfr
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//---------------------------------------------//
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typedef struct {
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/* 00 */ __RO __u32 DR00;
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/* 01 */ __RO __u32 DR01;
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/* 02 */ __RO __u32 DR02;
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/* 03 */ __RO __u32 DR03;
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/* 04 */ __RO __u32 DR04;
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/* 05 */ __RO __u32 DR05;
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/* 06 */ __RO __u32 DR06;
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/* 07 */ __RO __u32 DR07;
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/* 08 */ __RO __u32 DR08;
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/* 09 */ __RO __u32 DR09;
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/* 0a */ __RO __u32 DR10;
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/* 0b */ __RO __u32 DR11;
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/* 0c */ __RO __u32 DR12;
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/* 0d */ __RO __u32 DR13;
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/* 0e */ __RO __u32 DR14;
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/* 0f */ __RO __u32 DR15;
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/* 10 */ __RO __u32 RETI;
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/* 11 */ __RO __u32 RETE;
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/* 12 */ __RO __u32 RETX;
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/* 13 */ __RO __u32 RETS;
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/* 14 */ __RO __u32 SR04;
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/* 15 */ __RO __u32 PSR;
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/* 16 */ __RO __u32 CNUM;
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/* 17 */ __RO __u32 SR07;
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/* 18 */ __RO __u32 SR08;
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/* 19 */ __RO __u32 SR09;
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/* 1a */ __RO __u32 SR10;
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/* 1b */ __RO __u32 ICFG;
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/* 1c */ __RO __u32 USP;
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/* 1d */ __RO __u32 SSP;
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/* 1e */ __RO __u32 SP;
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/* 1f */ __RO __u32 PCRS;
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/* 20 */ __RW __u32 BPCON;
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/* 21 */ __RW __u32 BSP;
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/* 22 */ __RW __u32 BP0;
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/* 23 */ __RW __u32 BP1;
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/* 24 */ __RW __u32 BP2;
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/* 25 */ __RW __u32 BP3;
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/* 26 */ __WO __u32 CMD_PAUSE;
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/* */ __RO __u32 REV_30_26[0x30 - 0x26 - 1];
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/* 30 */ __RW __u32 PMU_CON;
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/* */ __RO __u32 REV_34_30[0x34 - 0x30 - 1];
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/* 34 */ __RW __u32 EMU_CON;
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/* 35 */ __RW __u32 EMU_MSG;
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/* 36 */ __RW __u32 EMU_SSP_H;
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/* 37 */ __RW __u32 EMU_SSP_L;
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/* 38 */ __RW __u32 EMU_USP_H;
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/* 39 */ __RW __u32 EMU_USP_L;
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/* */ __RO __u32 REV_3b_39[0x3b - 0x39 - 1];
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/* 3b */ __RW __u8 TTMR_CON;
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/* 3c */ __RW __u32 TTMR_CNT;
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/* 3d */ __RW __u32 TTMR_PRD;
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/* 3e */ __RW __u32 BANK_CON;
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/* 3f */ __RW __u32 BANK_NUM;
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/* 40 */ __RW __u32 ICFG00;
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/* 41 */ __RW __u32 ICFG01;
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/* 42 */ __RW __u32 ICFG02;
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/* 43 */ __RW __u32 ICFG03;
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/* 44 */ __RW __u32 ICFG04;
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/* 45 */ __RW __u32 ICFG05;
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/* 46 */ __RW __u32 ICFG06;
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/* 47 */ __RW __u32 ICFG07;
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/* 48 */ __RW __u32 ICFG08;
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/* 49 */ __RW __u32 ICFG09;
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/* 4a */ __RW __u32 ICFG10;
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/* 4b */ __RW __u32 ICFG11;
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/* 4c */ __RW __u32 ICFG12;
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/* 4d */ __RW __u32 ICFG13;
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/* 4e */ __RW __u32 ICFG14;
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/* 4f */ __RW __u32 ICFG15;
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/* 50 */ __RW __u32 ICFG16;
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/* 51 */ __RW __u32 ICFG17;
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/* 52 */ __RW __u32 ICFG18;
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/* 53 */ __RW __u32 ICFG19;
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/* 54 */ __RW __u32 ICFG20;
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/* 55 */ __RW __u32 ICFG21;
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/* 56 */ __RW __u32 ICFG22;
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/* 57 */ __RW __u32 ICFG23;
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/* 58 */ __RW __u32 ICFG24;
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/* 59 */ __RW __u32 ICFG25;
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/* 5a */ __RW __u32 ICFG26;
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/* 5b */ __RW __u32 ICFG27;
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/* 5c */ __RW __u32 ICFG28;
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/* 5d */ __RW __u32 ICFG29;
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/* 5e */ __RW __u32 ICFG30;
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/* 5f */ __RW __u32 ICFG31;
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/* 60 */ __RO __u32 IPND0;
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/* 61 */ __RO __u32 IPND1;
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/* 62 */ __RO __u32 IPND2;
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/* 63 */ __RO __u32 IPND3;
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/* 64 */ __RO __u32 IPND4;
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/* 65 */ __RO __u32 IPND5;
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/* 66 */ __RO __u32 IPND6;
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/* 67 */ __RO __u32 IPND7;
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/* 68 */ __WO __u32 ILAT_SET;
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/* 69 */ __WO __u32 ILAT_CLR;
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/* 6a */ __RW __u32 IPMASK;
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/* */ __RO __u32 REV_70_6a[0x70 - 0x6a - 1];
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/* 70 */ __RW __u32 ETM_CON;
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/* 71 */ __RO __u32 ETM_PC0;
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/* 72 */ __RO __u32 ETM_PC1;
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/* 73 */ __RO __u32 ETM_PC2;
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/* 74 */ __RO __u32 ETM_PC3;
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/* 75 */ __RW __u32 WP0_ADRH;
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/* 76 */ __RW __u32 WP0_ADRL;
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/* 77 */ __RW __u32 WP0_DATH;
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/* 78 */ __RW __u32 WP0_DATL;
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/* 79 */ __RW __u32 WP0_PC;
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} JL_TypeDef_q32DSP;
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#undef __RW
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#undef __RO
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#undef __WO
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#undef __u8
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#undef __u16
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#undef __u32
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typedef struct _CPU_REGS {
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unsigned int reti;
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unsigned int rets;
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unsigned int psr;
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unsigned int r0;
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unsigned int r1;
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unsigned int r2;
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unsigned int r3;
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unsigned int r4;
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unsigned int r5;
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unsigned int r6;
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unsigned int r7;
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unsigned int r8;
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unsigned int r9;
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unsigned int r10;
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unsigned int r11;
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unsigned int r12;
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unsigned int r13;
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unsigned int r14;
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unsigned int r15;
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} CPU_REGS;
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#define TICK_CON (q32DSP(0)->TTMR_CON)
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#define TICK_PRD (q32DSP(0)->TTMR_PRD)
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#define TICK_CNT (q32DSP(0)->TTMR_CNT)
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#define SOFT_CLEAR_PENDING (q32DSP(0)->ILAT_CLR)
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#define CPU_MSG (q32DSP(0)->EMU_MSG)
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#define CPU_CON (q32DSP(0)->EMU_CON)
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#endif
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//*********************************************************************************//
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// //
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// end of this module //
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// //
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//*********************************************************************************//
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